A reconfigurable design-for-debug infrastructure for SoCs

In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can...

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Bibliographic Details
Main Authors: Abramovici, Miron, Bradley, Paul, Dwarakanath, Kumar, Levin, Peter, Memmi, Gerard, Miller, Dave
Format: Conference Proceeding
Language:English
Subjects:
Applied computing > Physical sciences and engineering > Engineering
assertion-based debug
at-speed debug
Counting circuits
Design
Design engineering
Design for disassembly
Economics
Experimentation
Fabrics
Hardware
Hardware > Integrated circuits
Instruments
Observability
Permission
Silicon
Silicon debug
Time to market
Verification
what-if experiments
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Description
Summary:In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.
ISSN:0738-100X
DOI:10.1145/1146909.1146916