Use of C/C++ models for architecture exploration and verification of DSPs

Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural trade-offs that must be made for a practical implementation. The same models can be reused during the verification of the...

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Bibliographic Details
Main Authors: Brier, David, Mitra, Raj S.
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Algorithms
C/C++
Design
Digital signal processing
Documentation
Formal
Hardware > Communication hardware, interfaces and storage > Signal processing systems
Hardware > Electronic design automation > Hardware description languages and compilation
Hardware > Hardware validation > Functional verification
Hardware > Hardware validation > Functional verification > Simulation and emulation
Image processing
Instruments
Languages
Logic design
Pipelines
RTL
Signal design
Signal processing
Signal processing algorithms
Simulation
Verification
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Summary:Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural trade-offs that must be made for a practical implementation. The same models can be reused during the verification of the RTL subsequently developed, provided that various "hooks" which are desirable during the verification process are considered while creating these high level models. In addition, consideration must be given to the qualitative content of these high level models to permit an optimal verification flow allowing for compromise between features of the model and the completeness of the verification. Thus, high quality design and verification are achieved by the use of valid models and the valid use of models. In this paper, we describe our approach and show examples from a typical image processing application.
ISSN:0738-100X
DOI:10.1145/1146909.1146935