Federation: repurposing scalar cores for out-of-order instruction issue

Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better single-thread performance, a dedicated, larger core can help but comes at a large opportunity cost in t...

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Bibliographic Details
Main Authors: Tarjan, David, Boyer, Michael, Skadron, Kevin
Format: Conference Proceeding
Language:English
Subjects:
Aggregates
CMP
Computer science
Computer systems organization > Architectures > Parallel architectures > Multiple instruction, multiple data
Costs
Federation
Hardware
Instruction sets
multicore
Out of order
Permission
Throughput
VLIW
Yarn
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Summary:Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better single-thread performance, a dedicated, larger core can help but comes at a large opportunity cost in the number of scalar cores that could be provisioned instead. This paper proposes a way to repurpose a pair of scalar cores into a 2-way out-of-order issue core with minimal area overhead. "Federating" scalar cores in this way nevertheless achieves comparable performance to a dedicated out-of-order core and dissipates less power as well.
ISSN:0738-100X
DOI:10.1145/1391469.1391666