Power-efficient clustering via incomplete bypassing

Researchers have proposed clustered microarchitectures for performance and energy effciency. Typically, clustered microarchitectures offer fast, local bypassing between instructions within clusters but global bypasses are slower. Traditional clustered microarchitectures (TCM) are implemented by part...

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Bibliographic Details
Main Authors: Villasenor, Eric P., Seo, DaeHo, Thottethodi, Mithuna S.
Format: Conference Proceeding
Language:English
Subjects:
clustering
Computer architecture
Computer systems organization > Architectures
Delay
Energy consumption
incomplete bypass
Microarchitecture
Permission
power
Power engineering and energy
Power engineering computing
Registers
Voltage
voltage scaling
Wires
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Summary:Researchers have proposed clustered microarchitectures for performance and energy effciency. Typically, clustered microarchitectures offer fast, local bypassing between instructions within clusters but global bypasses are slower. Traditional clustered microarchitectures (TCM) are implemented by partitioning the register file and associated functional units to clusters. This paper demonstrates an alternate implementation - Incomplete bypass-based clustered microarchitecture (IBCM). IBCM reduces the length of bypass wires by 42.4% resulting in an 8.9% reduction of "Execute" stage delay. This delay reduction in the critical EX stage enables voltage scaling that results in significantly lower average power consumption (between 11.7% and 19.5% lower) while achieving identical performance.
DOI:10.1145/1393921.1394019