Evaluating design trade-offs in customizable processors

The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly focused on single criteria optimization, e.g., optimizing performance though custom instructions under pre-defined area...

Full description

Saved in:
Bibliographic Details
Main Authors: Bordoloi, Unmesh D., Huynh, Huynh Phung, Chakraborty, Samarjit, Mitra, Tulika
Format: Conference Proceeding
Language:English
Subjects:
Algorithm design and analysis
Approximation algorithms
ASIP
Computer systems organization > Embedded and cyber-physical systems
Computer systems organization > Real-time systems
Constraint optimization
Design automation
Embedded system
Multi-objective design space exploration
Pareto-optimal curve
Permission
Polynomials
Process design
Processor customization
Real time systems
Silicon
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:The short time-to-market window for embedded systems demands automation of design methodologies for customizable processors. Recent research advances in this direction have mostly focused on single criteria optimization, e.g., optimizing performance though custom instructions under pre-defined area constraint. From the designer's perspective, however, it would be more interesting if the conflicting trade-offs among multiple objectives (e.g., performance versus area) are exposed enabling an informed decision making. Unfortunately, identifying the optimal trade-off points turns out to be computationally intractable. In this paper, we present a polynomial-time approximation algorithm to systematically evaluate the design trade-offs. In particular, we explore performance-area trade-offs in the context of multitasking real-time embedded applications to be implemented on a customizable processor.
ISSN:0738-100X
DOI:10.1145/1629911.1629978