Design of cache memories for multi-threaded dataflow architecture

Cache memories have proven their effectiveness in the von Neumann architecture when localities of reference govern the execution loci of programs. A pure dataflow program, in contrast, contains no locality of reference since the execution sequence is enforced only by the availability of arguments. I...

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Bibliographic Details
Main Authors: Kavi, Krishna M., Hurson, A. R., Patadia, Phenil, Abraham, Elizabeth, Shanmugam, Ponnarasu
Format: Conference Proceeding
Language:English
Subjects:
Cache memory
Computational modeling
Computer architecture
Computer systems organization > Architectures > Other architectures > Data flow architectures
Computer systems organization > Architectures > Serial architectures > Pipeline computing
Data analysis
Distributed computing
Hardware > Integrated circuits > Semiconductor memory > Dynamic memory
Iron
Multithreading
Permission
Processor scheduling
Yarn
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Summary:Cache memories have proven their effectiveness in the von Neumann architecture when localities of reference govern the execution loci of programs. A pure dataflow program, in contrast, contains no locality of reference since the execution sequence is enforced only by the availability of arguments. Instruction locality may be enhanced if, dataflow programs are reordered. Enhancing the locality of data references in the dataflow architecture is a more challenging problem. In this paper we report our approaches to the design of instruction, data (operand) and I-Structure cache memories using the Explicit Token Store (ETS) model of dataflow systems. We will present the performance results obtained using various benchmark programs.
ISSN:1063-6897
2575-713X
DOI:10.1145/223982.224436