Multiscalar processors

Multiscalar processors use a new, aggressive implementation paradigm for extracting large quantities of instruction level parallelism from ordinary high level language programs. A single program is divided into a collection of tasks by a combination of software and hardware. The tasks are distribute...

Full description

Saved in:
Bibliographic Details
Main Authors: Sohi, Gurindar S., Breach, Scott E., Vijaykumar, T. N.
Format: Conference Proceeding
Language:English
Subjects:
Aggregates
Computer systems organization > Architectures > Parallel architectures
Computing methodologies > Modeling and simulation > Model development and analysis > Modeling methodologies
Concurrent computing
Counting circuits
General and reference > Cross-computing tools and techniques > Performance
Hardware
High level languages
Legged locomotion
Parallel processing
Program processors
Registers
Software and its engineering > Software notations and tools > Compilers
VLIW
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Multiscalar processors use a new, aggressive implementation paradigm for extracting large quantities of instruction level parallelism from ordinary high level language programs. A single program is divided into a collection of tasks by a combination of software and hardware. The tasks are distributed to a number of parallel processing units which reside within a processor complex. Each of these units fetches and executes instructions belonging to its assigned task. The appearance of a single logical register file is maintained with a copy in each parallel processing unit. Register results are dynamically routed among the many parallel processing units with the help of compiler-generated masks. Memory accesses may occur speculatively without knowledge of preceding loads or stores. Addresses are disambiguated dynamically, many in parallel, and processing waits only for true data dependences.This paper presents the philosophy of the multiscalar paradigm, the structure of multiscalar programs, and the hardware architecture of a multiscalar processor. The paper also discusses performance issues in the multiscalar model, and compares the multiscalar paradigm with other paradigms. Experimental results evaluating the performance of a sample of multiscalar organizations are also presented.
ISSN:1063-6897
2575-713X
DOI:10.1145/223982.224451