Technology mapping for large complex PLDs

In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consists of a large number of PLA-style logic blocks. Although the traditional synthesis approach for such devices uses two-level minimization, the complexity of recently-produced CPLDs has resulted...

Full description

Saved in:
Bibliographic Details
Main Authors: Anderson, Jason Helge, Brown, Stephen Dean
Format: Conference Proceeding
Language:English
Subjects:
Applied computing > Physical sciences and engineering > Engineering
Circuit synthesis
Computer systems organization > Dependable and fault-tolerant systems and networks
Digital circuits
Field programmable gate arrays
General and reference > Cross-computing tools and techniques > Performance
Hardware > Integrated circuits > Logic circuits > Combinational circuits
Hardware > Robustness
Hardware > Very large scale integration design > Application-specific VLSI designs
Logic arrays
Logic circuits
Logic devices
Logic functions
Mathematics of computing > Mathematical software
Networks > Network performance evaluation
Permission
Programmable logic arrays
Switches
Citations: Items that cite this one
Online Access:Request full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consists of a large number of PLA-style logic blocks. Although the traditional synthesis approach for such devices uses two-level minimization, the complexity of recently-produced CPLDs has resulted in a trend toward multi-level synthesis. We describe an approach that allows existing multi-level synthesis techniques [13] to be adapted to produce circuits that are well-suited for implementation in CPLDs. Our algorithm produces circuits that require up to 90% fewer logic blocks than the circuits produced by a recently-published algorithm.
DOI:10.1145/277044.277220