Gate matrix layout synthesis with two-dimensional folding

• Main Authors: Lin, I., Du, D. H. C., Yen, S. H. C.
• Format: Conference Proceeding
• Language: English
• Subjects: Hardware > Electronic design automation > Physical design (EDA) > Partitioning and floorplanning; Hardware > Electronic design automation > Physical design (EDA) > Placement; Hardware > Electronic design automation > Physical design (EDA) > Wire routing; Hardware > Very large scale integration design > Application-specific VLSI designs
• DOI: 10.1145/74382.74390

We have developed a gate matrix layout synthesis tool which utilizes folding technique on both rows and columns. The conventional interval graph model and the recently proposed dynamic net-list representation can not fully depict circuit schematics such as inter-net connections. The incomplete representations may mislead the search process for an optimal solution during the layout partitioning and the gate ordering phases. We propose a new graph-based model called hierarchical dynamic net-list to improve the schematic representation. Based on the new model, the folded layout area in the partitioning phase can be more accurately estimated. The new gate ordering algorithm proposed by us also takes the advantages of the hierarchical dynamic net-list model to handle the gate placement in the folded layouts. The experimental results show 12% to 15% improvement in layout area for small circuits and 30% improvement for a large circuit.