Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects

• Main Authors: Long, Changbo, Simonson, Lucanus J., Liao, Weiping, He, Lei
• Format: Conference Proceeding
• Language: English
• Subjects: Algorithm design and analysis; Applied sciences; Clocks; Delay; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Hardware > Electronic design automation > Physical design (EDA); Integrated circuit interconnections; Integrated circuits; Microprocessors; Permission; Piecewise linear techniques; Pipeline processing; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; System performance; Wire
• ISSN: 0738-100X
• DOI: 10.1145/996566.996742

Interconnect pipelining has a great impact on system performance, but has not been considered by automatic floorplanning. Consid-ering interconnect pipelining, we study the floorplanning optimiza-tion problem to minimize system CPI (cycles per instruction) and in turn maximize system performance. We develop an efficient table-based model called trajectory piece-wise linear (TPWL) model to estimate CPI with interconnect pipelining. Experiments show that the TPWL model differs from cycle-accurate simulations by less than 3.0%. We integrate this model with a simulated-annealing based floorplan optimization to obtain CPI-aware floorplanning. Compared to the conventional floorplanning to minimize area and wire length, our CPI-aware floorplanning can reduce CPI by up to 28.6% with a small area overhead of 5.69% under 100nm technol-ogy and obtain better results under 70nm technology. To the best of our knowledge, this paper is the first in-depth study on floorplan-ning optimization with consideration of interconnect pipelining.