Speculative dynamic vectorization

• Main Authors: Pajuelo, Alex, González, Antonio, Valero, Mateo
• Format: Conference Proceeding
• Language: English
• Subjects: Applied sciences; Computer science; control theory; systems; Computer systems; Computer systems and distributed systems. User interface; Computer systems organization > Architectures > Parallel architectures; Computer systems organization > Architectures > Parallel architectures > Systolic arrays; Electronics; Exact sciences and technology; Hardware; Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific instruction set processors; Software; Software and its engineering > Software notations and tools > General programming languages > Language features > Control structures
• ISSN: 1063-6897; 2575-713X
• DOI: 10.5555/545215.545246

Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also present in irregular or pointer-rich codes, for which the compiler is quite limited to discover it. In this paper we propose a microarchitecture extension in order to exploit SIMD parallelism in a speculative way. The idea is to predict when certain operations are likely to be vectorizable, based on some previous history information. In this case, these scalar instructions are executed in a vector mode. These vector instructions operate on several elements (vector operands) that are anticipated to be their input operands and produce a number of outputs that are stored on a vector register in order to be used by further instructions. Verification of the correctness of the applied vectorization eventually changes the status of a given vector element from speculative to non-speculative, or alternatively, generates a recovery action in case of misspeculation.The proposed microarchitecture extension applied to a 4-way issue superscalar processor with one wide bus is 19% faster than the same processor with 4 scalar buses to L1 data cache. This speed up is due basically to 1) the reduction in number of memory accesses, 15% for SpecInt and 20% for SpecFP, 2) the transformation of scalar arithmetic instructions into their vector counterpart, 28% for SpecInt and 23% for SpecFP, and 3) the exploitation of control independence for mispredicted branches.