Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design

Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolving state coding conflicts. The refinement process is generally done automatically using heuristics and often produces sub-optimal solutions, which have to be corrected manually. This paper presents a framework fo...

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Bibliographic Details
Main Authors: Madalinski, Agnes, Bystrov, Alex, Khomenko, Victor, Yakovlev, Alex
Format: Conference Proceeding
Language:English
Subjects:
Computing methodologies > Artificial intelligence > Search methodologies > Heuristic function construction
Hardware > Communication hardware, interfaces and storage > Buses and high-speed links
Hardware > Electronic design automation > High-level and register-transfer level synthesis
Online Access:Get full text
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Summary:Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolving state coding conflicts. The refinement process is generally done automatically using heuristics and often produces sub-optimal solutions, which have to be corrected manually. This paper presents a framework for an interactive refinement process aimed to help the designer. It is based on the visualization of conflict cores, i.e., sets of transitions causing coding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.
ISSN:1530-1591
DOI:10.5555/789083.1022842