Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture

• Main Authors: Rettberg, Achim, Zanella, Mauro, Lehmann, Thomas, Dierkes, Ulrich, Rustemeier, Carsten
• Format: Conference Proceeding
• Language: English
• Subjects: Hardware; Hardware > Emerging technologies > Analysis and design of emerging devices and systems > Emerging languages and compilers; Hardware > Integrated circuits > Logic circuits; Hardware > Very large scale integration design > Application-specific VLSI designs > Application specific instruction set processors; Software and its engineering > Software notations and tools > Compilers; Software and its engineering > Software notations and tools > General programming languages > Language features > Control structures
• DOI: 10.5555/942808.943985

The dynamic reconfiguration of controller implementations demand a specific processing architecture. Configurable elements are for example FPGAs. The price of FPGAs is mainly determined by the pin number. This means that it is costly to realize the large control systems with well-known architectures. In the case of reliable systems (e.g. steer-by-wire steering) a low pin count is not only a factor of cost but even so a factor for reliability. This paper presents a new synchronous, fully reconfigurable self-timed bit-serial and fully interlocked pipeline architecture called MACT. Due to bit-serial processing, bit-serial input and output systems with low pin count is required. We prove the usefulness of our architecture by an example implementation of a given problem on a Xilinx FPGA. The presented architecture is optimized for the use in embedded systems to control mechatronic systems, but can be also employed in other fields of application. So we furthermore present here the integration into a mechatronic design process.