Dynamic Voltage and Cache Reconfiguration for Low Power

• Main Authors: Nacul, Andre C., Givargis, Tony
• Format: Conference Proceeding
• Language: English
• Subjects: Hardware > Electronic design automation > High-level and register-transfer level synthesis; Hardware > Electronic design automation > High-level and register-transfer level synthesis > Hardware-software codesign; Hardware > Integrated circuits > Semiconductor memory; Hardware > Integrated circuits > Semiconductor memory > Dynamic memory; Software and its engineering > Software organization and properties > Contextual software domains > Operating systems > Process management > Scheduling; Theory of computation > Design and analysis of algorithms > Approximation algorithms analysis > Scheduling algorithms; Theory of computation > Design and analysis of algorithms > Online algorithms > Online learning algorithms > Scheduling algorithms; Theory of computation > Theory and algorithms for application domains > Machine learning theory > Reinforcement learning > Sequential decision making
• DOI: 10.5555/968879.969111

In this work, we propose a combined Dynamic Voltage Scaling (DVS) and Dynamic Cache Reconfiguration (DCR) online algorithm that dynamically adapts the processor speed (i.e., voltage) and the cache subsystem to the workload requirements for the purposes of saving energy. The workload is considered to be a set of tasks with real-time deadlines. Our online algorithm is invoked as part of the OS scheduler, which performs standard earliest deadline first (EDF) task scheduling first. Then, our online algorithm, determines an ideal voltage/cache configuration for the current executing task.