A new FPGA with 4/5-input LUT and optimized carry chain

• Published in: 半导体学报 2012, Vol.33 (7), p.113-120
• Main Author: Mao Zhidong Chen Liguang Wang Yuan Lai Jinmei
• Format: Article
• Language: Chinese
• Subjects: CMOS工艺; FPGA实现; LUT; Virtex; 优化; 资源配置; 进位链结构; 逻辑模块
• ISSN: 1674-4926

A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing interconnect resources. We also develop a new carry chain structure with an optimized critical path. Finally a newly designed configurable scan-chain is inserted. The circuit is fabricated in 0.13μm 1P8M 1.2/2.5/3.3 V logic CMOS process. The test results show a correct function of 4/5-input LUT and scan- chain, and a speedup in carry performance of nearly 3 times over current architecture in the same technology at the cost of an increase in total area of about 72.5%. Our results also show that the logic utilization of this work is better than that of a Virtex lI/Virtex 4/Virtex 5/Virtex 6/Virtex 7 FPGA when implemented using only 4-LUT and better than that of a Virtex lI/Virtex 4 FPGA when implemented using only 5-LUT.