Schedule refinement for homogeneous multi-core processors in the presence ofmanufacturing-caused heterogeneity

• Published in: 信息与电子工程前沿：英文版 2015, Vol.16 (12), p.1018-1033
• Main Author: Zhi-xiang CHEN Zhao-lin LI Shah CAO Fang WANG Jie ZHOU
• Format: Article
• Language: English
• ISSN: 2095-9184; 2095-9230

Multi-core homogeneous processors have been widely used to deal with computation-intensive embed- ded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturing process lead to a significant spread in the operating speeds of cores within homogeneous multi-core processors. Task scheduling approaches, which do not consider such heterogeneity caused by within-die variations, can lead to an overly pessimistic result in terms of performance. To realize an optimal performance according to the actual maximum clock frequencies at which cores can run, we present a heterogeneity-aware schedule refining （HASR） scheme by fully exploiting the heterogeneities of homogeneous multi-core processors in embedded domains. We analyze and show how the actual maximum frequencies of cores are used to guide the scheduling. In the scheme, representative chip operating points are selected and the corresponding optimal schedules are generated as candidate schedules. During the booting of each chip, according to the actual maximum clock frequencies of cores, one of the candidate schedules is bound to the chip to maximize the performancc. A set of applications are dcsigncd to cvaluatc the proposed scheme. Experimental results show that the proposed scheme can improve the performance by an average value of 22.2%, compared with the baseline schedule based on the worst case timing analysis. Compared with the conventional task scheduling approach based on the actual maximum clock frequencies, the proposed scheme also improves the performance by up to 12%.