Design of a Low-Power 20Gb/s 1:4 Demultiplexer in 0.18μm CMOS

• Published in: Chinese Journal of Electronics 2015-01, Vol.24 (1), p.71-75
• Main Authors: Pan, Min, Feng, Jun
• Format: Article
• Language: English
• Subjects: bit rate 20 Gbit/s; buffer circuits; clock; clock buffers; clocks; CMOS; CMOS logic circuits; CMOS process; complementary metal oxide semiconductor process; Demultiplexer; demultiplexing equipment; DEMUX; Dynamic; dynamic CMOS logic latch; dynamic-loading; flip‐flops; four‐channel oscillograph; frequency divider cell; frequency dividers; latch; logic; Low; low‐power electronics; low‐power multiphase clock demultiplexer; output rail‐to‐rail level; power; power dissipation; resistance 50 ohm; Single; single clock dynamic‐loading latch; size 0.18 mum; system integration; voltage 2 V; voltage 450 mV
• ISSN: 1022-4653; 2075-5597
• DOI: 10.1049/cje.2015.01.012

A low-power multi-phase clock 20Gb/s1:4 Demultiplexer(DEMUX) without inductors is designed in 0.18μm Complementary metal oxide semiconductor(CMOS) process. The 1:4 DEMUX includes two 1:2DEMUX cells, one 1/2 frequency divider cell, some data and clock buffers. A dynamic CMOS logic latch is used in the 1:2 DEMUX cell and a single clock dynamic-loading latch is used in the 1/2 frequency divider cell. These two kinds of logical structures not only reduce power dissipation and area, but also have an output rail-to-rail level. The rail-to-rail level can offer high noise margin and implement seamless connection without logic level conversion in system integration. The test results show that when the data rate of the input pseudorandom is 20Gb/s and the sequence length is 231-1, this 1:4 DEMUX can work well at a supply voltage of 2V. The output swing is 450 m V with external 50 Ohm load and the die size is 0.475×0.475mm2. The chip power dissipation is 86 m W, when four pads connect with a four-channel oscillograph.