Automatic verification of asynchronous circuits

Verifying asynchronous designs is difficult, since design errors may manifest themselves only under rare circumstances. This article describes how to model asynchronous designs as programs in synchronized transitions, a general-purpose hardware description language. The authors show how this represe...

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Published in:IEEE design & test of computers 1995, Vol.12 (1), p.24-31, Article 24
Main Authors: Lee, T.W.S., Greenstreet, M.R., Seger, C.-J.
Format: Article
Language:English
Subjects:
Asynchronous circuits
Circuit simulation
Delay
Hardware design languages
Latches
Logic
Signal design
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creator Lee, T.W.S.
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description Verifying asynchronous designs is difficult, since design errors may manifest themselves only under rare circumstances. This article describes how to model asynchronous designs as programs in synchronized transitions, a general-purpose hardware description language. The authors show how this representation facilitates rigorous, efficient verification.< >
doi_str_mv 10.1109/54.350687
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ispartof IEEE design & test of computers, 1995, Vol.12 (1), p.24-31, Article 24
issn 0740-7475
1558-1918
language eng
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source IEEE Electronic Library (IEL) Journals
subjects Asynchronous circuits
Circuit simulation
Delay
Hardware design languages
Latches
Logic
Signal design
title Automatic verification of asynchronous circuits
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