Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)

• Published in: IEEE transactions on very large scale integration (VLSI) systems 2013-09, Vol.21 (9), p.1632-1643, Article 1632
• Main Authors: Yoonmyung Lee, Daeyeon Kim, Jin Cai, Lauer, Isaac, Chang, Leland, Koester, Steven J., Blaauw, David, Sylvester, Dennis
• Format: Article
• Language: English
• Subjects: 7T SRAM; Applied sciences; Circuit properties; CMOS integrated circuits; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Hardware design languages; heterojunction tunneling transistors (HETT); Integrated circuits; Logic gates; low-power; MOSFETs; Oscillators, resonators, synthetizers; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Theoretical study. Circuits analysis and design; Transistors; Tunneling; tunneling transistor
• ISSN: 1063-8210; 1557-9999; 1557-9999
• DOI: 10.1109/TVLSI.2012.2213103

The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that an HETT-based ring oscillator (RO) shows a 9-19 times reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional mosfets, namely, asymmetric current flow and increased Miller capacitance, analyze their effect on circuit behavior, and propose methods to address them. HETT characteristics have the most dramatic impact on static random access memory (SRAM) operation and we propose a novel seven-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37 times reduction in leakage power compared to CMOS.