A novel IFPWM‐based all‐digital transmitter architecture and FPGA implementation

• Published in: International journal of circuit theory and applications 2025-01, Vol.53 (1), p.466-476
• Main Authors: Mehboob, Rahman, Haque, Muhammad Fahim Ul, Malik, Tahir, Johansson, Ted
• Format: Article
• Language: English
• Subjects: all‐digital transmitter (ADT); Field programmable gate arrays; FPGA; Frequencies; IF‐PWMT; MGT; M‐PWM; Pulse duration modulation; Radio frequency; RF‐PWMT; Software radio; Transmitters; Wireless communications
• ISSN: 0098-9886; 1097-007X
• DOI: 10.1002/cta.4123

The software‐defined radio (SDR) concept for wireless communications provides flexibility and simplicity, replacing most of the analog air interfaces. With all‐digital transmitters (ADT), the entire signal chain, from user input to frequency upconversion, can be implemented in the digital (programmable) domain, making it an ideal platform for SDR. ADTs depend heavily on the bitrate of the serializer to generate a specific frequency band with good Adjacent Channel Leakage Ratio (ACLR), however, the transmission frequency achieved is lower than half of the serializer's bitrate. In this paper, we present a scalable ADT architecture capable of generating higher transmission frequencies with state‐of‐the‐art comparable ACLR and relatively low implementation complexity. A modified Pulse‐Width Pulse‐Position Modulation (M‐PWPM) scheme, based on the RF‐PWM principle, is derived, which provides an improved ACLR and Error Vector Magnitude (EVM). The proposed transmitter architecture implemented on an Field‐Programmable Gate Array (FPGA) achieves ACLR of 32 dB and EVM below 2% at 14.72 GHz Tx frequency for a 20 MHz LTE signal. The obtained transmission frequency was achieved using a serializer operating at 28 Gbps, which is for the first time beyond the half of the serializer's bitrate. The proposed ADT architecture has the potential to be used with serializers beyond 28 Gbps bitrate, hence, achieving even higher transmission frequencies. In an ADT, the entire signal chain, from user input and baseband processing to frequency up‐conversion, is in the digital domain, providing significant advantages over transmitters having analog front‐end. In this paper, we present an ADT architecture employing heterodyne principle that achieves a transmission frequency beyond half of the serializer bit‐rate and show its implementation on an FPGA having a serializer bit‐rate of upto 28 Gbps.