A Study of Self‐Dithering for Fractional‐N PLL

The fractional‐N phase‐locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the modulator when the input value is fixed, and as a resu...

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Bibliographic Details
Published in:Electronics and communications in Japan 2015-01, Vol.98 (1), p.9-14
Main Authors: Kato, Yuji, Ioka, Eri, Matsuya, Yasuyuki
Format: Article
Language:eng ; jpn
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Summary:The fractional‐N phase‐locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self‐dithering fractional‐N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.
ISSN:1942-9533
1942-9541
DOI:10.1002/ecj.11606