GaN HEMT and MMIC development at Fraunhofer IAF: performance and reliability

• Published in: Physica status solidi. A, Applications and materials science Applications and materials science, 2009-06, Vol.206 (6), p.1215-1220
• Main Authors: Waltereit, P., Bronner, W., Quay, R., Dammann, M., Kiefer, R., Müller, S., Musser, M., Kühn, J., Raay, F. van, Seelmann, M., Mikulla, M., Ambacher, O., Rijs, F. van, Rödle, T., Riepe, K.
• Format: Article
• Language: English
• Subjects: 85.30.De; 85.30.Tv; Applied sciences; Circuit properties; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronics; Exact sciences and technology; Integrated circuits; Microelectronic fabrication (materials and surfaces technology); Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Transistors
• ISSN: 1862-6300; 1862-6319
• DOI: 10.1002/pssa.200880774

We present a systematic study of epitaxial growth, processing technology, device performance and reliability of our GaN HEMTs and MMICs manufactured on 3 inch SiC substrates. Epitaxy and processing are optimized for both performance and reliability. The deposition of the AlGaN/GaN HEMT epitaxial structures is designed for low background carrier concentration and a low trap density in order to simultaneously achieve a high buffer isolation and low DC to RF dispersion. Device fabrication is performed using standard processing techniques involving both electron‐beam and stepper lithography. Gate lengths of 250 nm and 500 nm are employed for 10 GHz and 2 GHz applications, respectively. The developed HEMTs demonstrate excellent high‐voltage stability, high power performance and large power added efficiencies. Devices exhibit two‐terminal gate–drain breakdown voltages in excess of 160 V (current criterion 1 mA/mm) across the entire 3 inch wafer with parasitic gate and drain currents well below 1 mA/mm when biased up to 80 V drain bias under pinch‐off conditions. Load‐Pull measurements at 2 GHz on 800 μm gate width devices return a well‐behaved relationship between bias‐voltage and output‐power as well as power‐added‐efficiencies beyond 60% up to UDS = 100 V. For a drain bias of 100 V an output‐power‐density around 22 W/mm with 26 dB linear gain is obtained. On large devices (32 mm gate width packaged in industry‐standard ceramic packages) an output power beyond 100 W is achieved with a PAE above 50% and a linear gain around 15 dB. Dual‐stage MMICs in microstrip transmission line technology yield a power added efficiency of 40% at 8.56 GHz for a power level of 11 W. A single‐stage MMIC yields a PAE of 46% with 7 W of output power at VDS = 28 V. Reliability is tested on HEMT devices having a gate periphery of 8 × 60 μm at an operating bias of 50 V under both DC and RF conditions. About 10% drain‐current change under DC‐stress (50 mA/mm) is observed after more than 1000 h of operation with an extrapolated drain‐current degradation below 20% after 200000 h (more than 20 years) of operation. Under RF stress (2 GHz, 1 dB compression) the observed change in output power density is below 0.2 dB after more than 1000 h. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)