An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip

• Published in: Software, practice & experience practice & experience, 2012-07, Vol.42 (7), p.877-890
• Main Authors: Lafi, Walid, Lattard, Didier, Jerrya, Ahmed
• Format: Article
• Language: English
• Subjects: 3D integration; MPSoC; network-on-chip
• ISSN: 0038-0644; 1097-024X
• DOI: 10.1002/spe.1150

SUMMARY Three‐dimensional networks‐on‐chip (3D NoC) are rising as a good approach to well managed complex interconnections in 3D multi‐processor system‐on‐chip (MPSoC). This paper introduces a new router in order to enhance throughput and latency compared to classic 3D mesh NoC. The proposed router is hierarchical as it is composed of two completely decoupled modules: one for inter‐layer communication and one for intra‐layer communication. It is fully implemented in asynchronous logic to allow low latency transfer. Synthesis and extrapolation results show that the hierarchical router is competitive with the classic 3D mesh in terms of area and power. Throughput and latency evaluation is performed using a SystemC‐TLM NoC simulator. Simulations' results show that the proposed hierarchical router can outperform the 3D mesh by more than 25% in terms of throughput and latency in the case of transpose traffic. Copyright © 2012 John Wiley & Sons, Ltd.