QPACE: power-efficient parallel architecture based on IBM PowerXCell 8i

• Published in: Computer science (Berlin, Germany) Germany), 2010-09, Vol.25 (3-4), p.149-154
• Main Authors: Baier, H., Boettiger, H., Drochner, M., Eicker, N., Fischer, U., Fodor, Z., Frommer, A., Gomez, C., Goldrian, G., Heybrock, S., Hierl, D., Hüsken, M., Huth, T., Krill, B., Lauritsen, J., Lippert, T., Maurer, T., Mendl, B., Meyer, N., Nobile, A., Ouda, I., Pivanti, M., Pleiter, D., Ries, M., Schäfer, A., Schick, H., Schifano, F., Simma, H., Solbrig, S., Streuer, T., Sulanke, K.-H., Tripiccione, R., Vogt, J.-S., Wettig, T., Winter, F.
• Format: Article
• Language: English
• Subjects: Applied sciences; Computer Hardware; Computer Science; Computer science; control theory; systems; Computer Systems Organization and Communication Networks; Data Structures and Information Theory; Exact sciences and technology; Software; Software engineering; Software Engineering/Programming and Operating Systems; Special Issue Paper; Theory of Computation
• ISSN: 1865-2034; 1865-2042
• DOI: 10.1007/s00450-010-0122-4

QPACE is a novel massively parallel architecture optimized for lattice QCD simulations. Each node comprises an IBM PowerXCell 8i processor. The nodes are interconnected by a custom 3-dimensional torus network implemented on an FPGA. The architecture was systematically optimized with respect to power consumption. This put QPACE in the number one spot on the Green500 List published in November 2009. In this paper we give an overview of the architecture and highlight the steps taken to improve power efficiency.