Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

• Published in: Microsystem technologies 2012-08, Vol.18 (7-8), p.1057-1063
• Main Authors: Vasilache, D., Colpo, S., Giacomozzi, F., Ronchin, S., Gennaro, S., Qureshi, A. Q. A., Margesin, B.
• Format: Article
• Language: English
• Subjects: Applied sciences; Circuit properties; Electric, optical and optoelectronic circuits; Electronics; Electronics and Microelectronics; Engineering; Exact sciences and technology; Instrumentation; Mechanical Engineering; Microwave circuits, microwave integrated circuits, microwave transmission lines, submillimeter wave circuits; Nanotechnology; Technical Paper
• ISSN: 0946-7076; 1432-1858
• DOI: 10.1007/s00542-012-1438-8

This paper reports a method on the manufacturing of through silicon wafer via holes with tapered walls by Deep Reactive Ion Etching using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window. The optimized process was used to obtain via’s with a good control over the walls angles for two etching windows sizes (100 and 20 μm respectively) on 300 μm thick silicon wafers. After process optimization, a deviation smaller than 10% of the manufactured via holes across the wafers was observed for the designed walls angles of 11.3° and 21.8°. Barrier and seed layers were deposited in via’s performed by Physical Vapor Deposition techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via’s.