A CMOS 3.2 Gb/s serial link transceiver, using a new PWAM scheme

• Published in: Analog integrated circuits and signal processing 2012-06, Vol.71 (3), p.421-432
• Main Authors: Ghaderi, Noushin, Hadidi, Khayrollah, Khoei, Abdollah
• Format: Article
• Language: English
• Subjects: Circuits and Systems; Electrical Engineering; Engineering; Signal,Image and Speech Processing
• ISSN: 0925-1030; 1573-1979
• DOI: 10.1007/s10470-011-9767-6

In this article, a 3.2 Gb/s serial link transceiver, that can be implemented in 0.35 μm CMOS technology is presented. In this transceiver a new multi-level pulse-width-amplitude modulation technique is used. The symbol rate is reduced, while the minimum pulse width (PW) is increased considerably, using the proposed modulation. The PW is larger than the conventional NRZ data format, with PW of Tb, so the ISI will be improved. The multiphase output of a three stage ring oscillator VCO in the PLL is used to modulate and to demodulate the signal. A new charge pump circuit is also introduced to decrease the mismatch between up and down paths. The peak to peak jitter of recovered clock is 21 ps at 800 MHz. The recovered data has the peak to peak jitter of 51 ps. The transmitter and receiver power consumption is 220 and 35 mW, respectively.