Accuracy improvement of the output impedance model for capacitive down-converters

Contemporary models fail to include the influence of the output buffer capacitor size on the performance of capacitive DC–DC converters. This letter examines the relevance of this dependency and shows how to adapt existing models in order to include it. The improved model is verified mathematically...

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Bibliographic Details
Published in:Analog integrated circuits and signal processing 2012-07, Vol.72 (1), p.271-277
Main Authors: Van Breussegem, Tom, Steyaert, Michiel
Format: Article
Language:English
Subjects:
Circuits and Systems
Electrical Engineering
Engineering
Mixed Signal Letter
Signal,Image and Speech Processing
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Summary:Contemporary models fail to include the influence of the output buffer capacitor size on the performance of capacitive DC–DC converters. This letter examines the relevance of this dependency and shows how to adapt existing models in order to include it. The improved model is verified mathematically for down-converters, by means of Spice simulations and based on measurements of silicon integrated prototypes. Measurements demonstrate an accuracy improvement of up to 30 % compared with the conventional model.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-012-9858-z