VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications

• Published in: Journal of signal processing systems 2015-02, Vol.78 (2), p.199-208
• Main Authors: Lee, Yu-Hsuan, Pan, Cheng-Wei
• Format: Article
• Language: English
• Subjects: Circuits and Systems; Computer Imaging; Electrical Engineering; Engineering; Image Processing and Computer Vision; Pattern Recognition; Pattern Recognition and Graphics; Signal,Image and Speech Processing; Vision
• ISSN: 1939-8018; 1939-8115
• DOI: 10.1007/s11265-013-0815-6

The Dedicated Short-Range Communication (DSRC) is an emerging standard to push the vehicular communication into modern automotive industry. The DSRC standard generally applies FM0 and Manchester to reach DC-balance enhancing the signal reliability. However, the intrinsic unbalance computation load between FM0 and Manchester makes their VLSI architecture with poor hardware utilization. In this paper, the reuse-oriented Boolean simplification (ROBS) technique is proposed to overcome this problem. The ROBS technique constructs the balance-type architecture to improve the hardware utilization rate (HUR) from 50 % to 90 %. The analysis of how the clock-skew affects the balance-type architecture is also discussed. This work is realized by 0.18um 1P6M CMOS technology with cell-based design flow. The gate count is 25.61, which is normalized to a 2-input NAND gate. The power consumption is 6.58uW@27MHz for FM0 encoding and 6.85uW@27MHz for Manchester encoding. The encoding capability is up to 27 Mbps that can fully support the DSRC standards of America, Europe and Japan.