Reconfigurable Interpolation Architecture for Multistandard Video Decoding

• Published in: Journal of signal processing systems 2016-08, Vol.84 (2), p.251-264
• Main Authors: Lee, Gwo Giun, Tai, Tzu-Chiang, Yang, Wei-Chiao, Chen, Chun-Fu, Huang, Chun-Hsi
• Format: Article
• Language: English
• Subjects: Circuits and Systems; Computer Imaging; Electrical Engineering; Engineering; Image Processing and Computer Vision; Pattern Recognition; Pattern Recognition and Graphics; Signal,Image and Speech Processing; Vision
• ISSN: 1939-8018; 1939-8115
• DOI: 10.1007/s11265-015-1053-x

Subpixel interpolation is an essential part to increase coding efficiency in many video compression standards. There arises the need to support the interpolation processes in multiple standards. In this paper, we propose a reconfigurable interpolation architecture for video decoding in MPEG-2, MPEG-4, and AVC/H.264. To reduce the hardware complexity and improve the operation efficiency, we analyze the commonality of interpolation filters for target standards. To have efficient memory access, we present a method to arrange data properly in cache memory. Our interpolator adopts the high throughput separated 1-D design and can be adapted to each target standard by using reconfigurable interpolation filters. We design the reconfigurable interpolation filter based on the commonality analysis so that it has very simple structure. The implementation results show that our interpolator consuming 31.7K gates can support processing video with resolution of 1920 × 1088 and frame rate of 30 frames/s. This compares very favorably with the existing architectures in silicon area and performance.