Hardware Architecture for RSA Cryptography Based on Residue Number System

A parallel architecture for efficient hardware implementation of Rivest Shamir Adleman （RSA） cryptog- raphy is proposed. Residue number system （RNS） is introduced to realize high parallelism, thus all the elements under the same base are independent of each other and can be computed in parallel. Mor...

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Bibliographic Details
Published in:Transactions of Tianjin University 2012-08, Vol.18 (4), p.237-242
Main Author: 郭炜 刘亚灵 白松辉 魏继增 孙达志
Format: Article
Language:English
Subjects:
Engineering
Humanities and Social Sciences
Mechanical Engineering
multidisciplinary
RSA加密
Science
体系结构
余数系统
密码学
平行度
并行计算
硬件实现
硬件架构
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Description
Summary:A parallel architecture for efficient hardware implementation of Rivest Shamir Adleman （RSA） cryptog- raphy is proposed. Residue number system （RNS） is introduced to realize high parallelism, thus all the elements under the same base are independent of each other and can be computed in parallel. Moreover, a simple and fast base trans- formation is used to achieve RNS Montgomery modular multiplication algorithm, which facilitates hardware imple- mentation. Based on transport triggered architecture （TTA）, the proposed architecture is designed to evaluate the per- formance and feasibility of the algorithm. With these optimizations, a decryption rate of 106 kbps can be achieved for 1 024-b RSA at the frequency of 100 MHz.
ISSN:1006-4982
1995-8196
DOI:10.1007/s12209-012-1902-7