Crystal damage and the properties of implanted p- n junctions in silicon

• Published in: Solid-state electronics 1978-01, Vol.21 (5), p.721-727
• Main Author: Zandveld, P.
• Format: Article
• Language: English
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/0038-1101(78)90004-7

The influence of crystal damage on the properties of implanted p- n junctions has been studied by variation of the amount of initial damage, variation of the recovery process, and variation of the residual damage. This was done by carrying out implantations at - 196, 25 and 700°C with 10 15 B +/cm 2 at an energy of 50 keV, and at 25°C with 10 15 BF 2 + at an energy of 250 keV and 10 15 Ga +/cm 2 at an energy of 70 keV. Substrate orientations of both 〈111〉 and 〈100〉 were used, and annealing was done in a temperature range between 400 and 1100°C. Gettered as well as non-gettered slices were used for 〈111〉 oriented substrates. The diode properties were analyzed with the aid of Shockley-Read-Hall recombination statistics. Depending upon crystal history and processing, different traps are found to dominate the reverse current. Traps caused by the gettering of contamination as well as those caused by the damage itself play a role. The number of traps is found to be smaller than 10 12/cm 3 for well annealed diodes, resulting in a reverse current density of 0.2 nA/cm 2 at 1 V reverse bias.