A network of transputers to emulate a parallel symbolic processor

This paper deals with the N-ARCH project developed at the University of Lille and its implementation on an INMOS transputers network. The aim of this project is the design of a parallel architecture with non-Von Neumann control modes and suited to declarative languages processing [Tour 87]. A first...

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Bibliographic Details
Published in:Microprocessing and microprogramming 1988-03, Vol.23 (1), p.149-152
Main Authors: Goncalves, G, Lecouffe, M.P, Toursel, B, Niar, S
Format: Article
Language:English
Online Access:Get full text
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Summary:This paper deals with the N-ARCH project developed at the University of Lille and its implementation on an INMOS transputers network. The aim of this project is the design of a parallel architecture with non-Von Neumann control modes and suited to declarative languages processing [Tour 87]. A first section describes the main characteristics of the architecture. A second part details the basic functions and the structure of a network node. A final part presents a prototype implementation of N-ARCH based on a network of transputers.
ISSN:0165-6074
DOI:10.1016/0165-6074(88)90347-X