VLSI testing with CAD-linked electron beam test system

Two approaches for efficient fault diagnosis are proposed where only CAD layout data is available in the CAD-linked electron beam test system. One is a circuit logical function extraction method from the CAD layout data. In the method, after extracting transistor-level circuit data in a unit of a pr...

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Bibliographic Details
Published in:Microelectronic engineering 1996-02, Vol.31 (1), p.319-330
Main Authors: Nakamae, Koji, Miura, Katsuyoshi, Fujioka, Hiromu
Format: Article
Language:English
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Summary:Two approaches for efficient fault diagnosis are proposed where only CAD layout data is available in the CAD-linked electron beam test system. One is a circuit logical function extraction method from the CAD layout data. In the method, after extracting transistor-level circuit data in a unit of a primitive logic gate from a flat structured CAD layout data, the data are translated to higher cell-level data automatically in order to trace a fault hierarchically. The other is a hierarchical fault tracing method for a hierarchically structured CAD layout data. The method allows us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit da a consistent manner independent of circuit functions even when the cell data and the transistor-level circuit data exist in a level as a mixture.
ISSN:0167-9317
1873-5568
DOI:10.1016/0167-9317(95)00354-1