Readout electronics development for the ATLAS silicon tracker

• Published in: Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment Accelerators, spectrometers, detectors and associated equipment, 1995-06, Vol.360 (1-2), p.193-196
• Main Authors: Borer, K., Beringer, J., Anghinolfi, F., Aspell, P., Chilingarov, A., Jarron, P., Heijne, E.H.M., Santiard, J.C., Verweij, H., Goessling, C., Lisowski, B., Reichold, A., Bonino, R., Clark, A.G., Kambara, H., La Marra, D., Leger, A., Wu, X., Richeux, J.P., Taylor, G.N., Fedotov, M., Kuper, E., Velikzhanin, Yu, Campbell, D., Murray, P., Seller, P.
• Format: Article
• Language: English
• ISSN: 0168-9002; 1872-9576
• DOI: 10.1016/0168-9002(94)01715-8

We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints.