Comparison of different on-chip ESD protection structures in a 0.35 μm CMOS technology

In nowadays submicron technologies, Electrostatic Discharges (ESD) are one of the major threat for the reliability of ICs. The aim of this paper is to demonstrate that a very good ESD protection level can be achieved provided we can insure a uniform triggering of multifinger NMOS protection devices....

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Bibliographic Details
Published in:Microelectronics and reliability 1997-10, Vol.37 (10), p.1537-1540
Main Authors: Richier, C., Maene, N., Mabboux, G., Bellens, R.
Format: Article
Language:English
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Testing, measurement, noise and reliability
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Summary:In nowadays submicron technologies, Electrostatic Discharges (ESD) are one of the major threat for the reliability of ICs. The aim of this paper is to demonstrate that a very good ESD protection level can be achieved provided we can insure a uniform triggering of multifinger NMOS protection devices. This can be done by a gate coupling to the drain, either by a capacitance or by a zener diode. Human Body Model (HBM) and Charged Device Model (CDM) test results, as well as Transmission Line Measurement (TLM) and light emission results support this finding.
ISSN:0026-2714
1872-941X
DOI:10.1016/S0026-2714(97)00103-0