Impact of geometrical scaling on parasitic pnp bipolar transistor in N-well, 0.25 μm CMOS devices and its effect on latchup immunity

This paper presents a detailed analysis of latchup dependence on geometrical dimensions of N-well, 0.25 μm complementary metal-oxide silicon (CMOS) devices with 50 Ågate oxide using simulation and experiment. Simulation results show that as dimensions continue to shrink, the traditionally accepted v...

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Bibliographic Details
Published in:Microelectronics and reliability 1998, Vol.38 (10), p.1621-1626
Main Authors: Leong, Kam-Chew, Lin, Po-Ching, Ho, Hok-Min, Gan, Chock-Ming, Chan, Lap
Format: Article
Language:English
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Testing, measurement, noise and reliability
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Summary:This paper presents a detailed analysis of latchup dependence on geometrical dimensions of N-well, 0.25 μm complementary metal-oxide silicon (CMOS) devices with 50 Ågate oxide using simulation and experiment. Simulation results show that as dimensions continue to shrink, the traditionally accepted vertical parasitic pnp bipolar transistor becomes a lateral device. This observed result is very significant since increasing the N-well junction depth no longer guarantees improvement in latchup immunity. Experimental data shows that variation in p+ emitter to N-well edge spacing ( d plat) does not affect latchup characteristics as long as d plat is far greater than d pver, the difference between the N-well and p+ diffusion junction depth.
ISSN:0026-2714
1872-941X
DOI:10.1016/S0026-2714(98)00059-6