Electrical characterization of copper interconnects with end-of-roadmap feature sizes

The metallization of trenches with end-of-roadmap feature sizes using a damascene approach is demonstrated. By applying an adapted spacer technique, narrow trenches were fabricated in an oxide-based intermetal dielectric, filled with barrier metal and Cu and subsequent CMP of the copper/barrier bi-l...

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Bibliographic Details
Published in:Solid-state electronics 2003-07, Vol.47 (7), p.1233-1236
Main Authors: Schindler, G, Steinlesberger, G, Engelhardt, M, Steinhögl, W
Format: Article
Language:English
Subjects:
Cu-damascene
Interconnect
Maximum current density
Resistivity
Size effect
Temperature dependence
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Summary:The metallization of trenches with end-of-roadmap feature sizes using a damascene approach is demonstrated. By applying an adapted spacer technique, narrow trenches were fabricated in an oxide-based intermetal dielectric, filled with barrier metal and Cu and subsequent CMP of the copper/barrier bi-layer. Thus damascene metal lines with widths down to 40 nm and aspect ratios exceeding 4 could be fabricated. These metal lines could be characterized electrically up to a length of almost 10 cm. The data show an increase of resistivity for small line widths, which can be explained by surface scattering. The surface effects can also be seen in the temperature dependence of the resistance. The maximum current density was shown to exceed those of todays interconnect lines by a factor of 2, exceeding the ITRS requirements for the maximum current density of such structures.
ISSN:0038-1101
1879-2405
DOI:10.1016/S0038-1101(03)00042-X