Understanding the limits of ultrathin SiO2 and Si-O-N gate dielectrics for sub-50 nm CMOS

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Bibliographic Details
Published in:Microelectronic engineering 1999-09, Vol.48 (1-4), p.25-30
Main Authors: GREEN, M. L, SORSCH, T. W, TIMP, G. L, MULLER, D. A, WEIR, B. E, SILVERMAN, P. J, MOCCIO, S. V, KIM, Y. O
Format: Article
Language:English
Subjects:
Applied sciences
Electronics
Exact sciences and technology
Microelectronic fabrication (materials and surfaces technology)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
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ISSN:0167-9317
1873-5568
DOI:10.1016/s0167-9317(99)00330-5