VHDL behavioural modelling of pipeline analog to digital converters

• Published in: Measurement 2002, Vol.31 (1), p.47-60
• Main Authors: Acosta, Antonio J., Peralı́as, Eduardo J., Rueda, Adoración, Huertas, José L.
• Format: Article
• Language: English
• Subjects: Analog to digital converter modelling; Analog-digital conversion, digital-analog conversion, pcm coding; Applied sciences; Circuits and circuit components; Circuits ans circuit components; Computer modeling and simulation; Computers in experimental physics; Electrical and electronic components, instruments and techniques; Exact sciences and technology; Information, signal and communications theory; Instruments, apparatus, components and techniques common to several branches of physics and astronomy; Physics; Pipeline ADCs; Signal and communications theory; Telecommunications and information theory; VHDL
• ISSN: 0263-2241; 1873-412X
• DOI: 10.1016/S0263-2241(01)00014-8

This paper describes a VHDL implementation of a behavioural model for pipeline analog to digital converters (ADCs). The goal is using this VHDL description to facilitate the synthesis of the digital part, which in our example includes digital correction, digital calibration, and control of the ADC testing modes. Among other aspects of general interest, we will show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. As an application example, an ADC of 10-bits and 10 MSamples/s has been modelled and simulated. Results from these high level simulations carried out using QuickHDL in Mentor Graphics are compared with those obtained experimentally from a silicon prototype, validating the suitability of the model.