Gate oxide integrity dependence on substrate characteristics and SiO2 thickness

• Published in: Materials science in semiconductor processing 2001-02, Vol.4 (1-3), p.145-148
• Main Authors: Bonoli, F., Godio, P., Borionetti, G., Falster, R.
• Format: Article
• Language: English
• Subjects: Dielectric breakdown; Silicon dioxide; Voids
• ISSN: 1369-8001; 1873-4081
• DOI: 10.1016/S1369-8001(00)00152-9

Gate oxide integrity (GOI) has been investigated for a wide range of oxide thicknesses, from 5 to 50nm. Silicon substrates containing voids of number densities along with defect-free (perfect) polished and epitaxial wafers were tested. Oxide reliability was monitored by linear ramped field tests at variable ramp rate and by constant current and field tests using a doped polysilicon gate as the cathode. The field and time parameters characterizing the distributions of each breakdown mode have been extracted by Weibull analysis. In general, more than one mode of breakdown is found in a given sampled substrate type. The average field of the breakdown shifts to higher fields with decreasing oxide thickness. In the void-related mode, a constant countable number of defects for a given substrate type are “activated” at sufficiently high fields independent of oxide thickness. Void-free epi and “perfect” substrates show a single, non-intrinsic breakdown mode. This mode is also found in the void containing materials in the part of their distribution, unaffected by voids.