Electronic transport properties of single-crystal silicon nanowires fabricated using an atomic force microscope

• Published in: Physica. E, Low-dimensional systems & nanostructures Low-dimensional systems & nanostructures, 2002-03, Vol.13 (2), p.999-1002
• Main Authors: Clément, N, Tonneau, D, Dallaporta, H, Bouchiat, V, Fraboulet, D, Mariole, D, Gautier, J, Safarov, V
• Format: Article
• Language: English
• Subjects: AFM; Lithography; Silicon nanostructures; Silicon-on-insulator
• ISSN: 1386-9477; 1873-1759
• DOI: 10.1016/S1386-9477(02)00288-6

We present electrical characterization of silicon nanowires made from ultrathin silicon-on-insulator (SOI) using a lithography process based on an atomic force microscope (AFM). SOI wafers were first thinned, prepatterned and doped using conventional microelectronics processes in order to elaborate contact leads and pads. Between contacts, the upper Si was further thinned down to 15 nm and n-doped by arsenic implantation. The Si top layer is then locally patterned using local oxidation induced under the biased tip of the AFM. The active part of the device is finally obtained by silicon selective wet etching using the AFM-made oxide pattern as a mask. This technique was used to study electrical transport through silicon wires with sub- 1000 nm 2 cross-section. The implementation of both side gates and backgate control allowed to test a full device which acts at room temperature as a field effect transistor. Current densities as high as 2×10 5 A/ cm 2 can be switched off by lateral gate control. At low temperatures, aperiodic oscillations of the nanowire current are observed while the gate voltage is swept. This behavior is attributed to potential variations along the wire caused by random fluctuations of dopants.