The AB-CCII, a novel adaptive biasing LV-LP current conveyor architecture

We present a low voltage low power architecture for an integrated current conveyor (CCII) topology, designed to decrease the stand-by power dissipation without affecting the CCII transient performance. In the proposed circuit, implemented in a standard AMS 0.35um CMOS technology, an extra current fl...

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Bibliographic Details
Published in:International journal of electronics and communications 2017-09, Vol.79, p.301-306
Main Authors: Stornelli, V., Pantoli, L., Ferri, G., Liberati, L., Centurelli, F., Monsurrò, P., Trifiletti, A.
Format: Article
Language:English
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Summary:We present a low voltage low power architecture for an integrated current conveyor (CCII) topology, designed to decrease the stand-by power dissipation without affecting the CCII transient performance. In the proposed circuit, implemented in a standard AMS 0.35um CMOS technology, an extra current flows into the circuit only when an input voltage variation occurs (through the adaptive biasing technique), so improving the transient response speed without a substantial increase of the average power consumption. Simulation results confirm the expected theoretical considerations.
ISSN:1434-8411
1618-0399
DOI:10.1016/j.aeue.2017.06.022