Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS

The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a...

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Bibliographic Details
Published in:International journal of electronics and communications 2018-08, Vol.92, p.30-35
Main Authors: Avoli, Matteo, Centurelli, Francesco, Monsurrò, Pietro, Scotti, Giuseppe, Trifiletti, Alessandro
Format: Article
Language:English
Subjects:
DDA
Instrumentation amplifier
Low power
Neural recording
Sub-threshold CMOS
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Summary:The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a differential-difference amplifier (DDA) whose differential output current drives a fully differential, high-resistance, transimpedance stage, with an embedded common-mode feedback loop to increase the CMRR. This stage is followed by a differential-to-single-ended output amplifier. Low-power operation has been achieved by exploiting sub-threshold operation of MOS transistors and adopting a supply voltage of 1 V. Simulation results in a commercial 65 nm CMOS technology show a 1 Hz to 5 kHz bandwidth, a CMRR higher than 120 dB, an input referred noise of 8.1 μVrms and a power consumption of 1.12 μW.
ISSN:1434-8411
1618-0399
DOI:10.1016/j.aeue.2018.05.014