An energy efficient symmetrical DAC switching scheme for single-ended SAR ADCs with zero reset energy and a 3-stage common-mode insensitive regenerative comparator

• Published in: International journal of electronics and communications 2022-12, Vol.157, p.154421, Article 154421
• Main Authors: Pahlavanzadeh, Hadi, Karami, Mohammad Azim
• Format: Article
• Language: English
• Subjects: Analog-to-Digital-Converter (ADC); Comparator; Digital-to-Analog-Converter (DAC); Successive Approximation Register (SAR)
• ISSN: 1434-8411; 1618-0399
• DOI: 10.1016/j.aeue.2022.154421

A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme suitable for single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is proposed in this paper. The proposed scheme synthesizes two reference voltages Vref and Vq to generate relevant voltage levels. The reference voltage Vq is a quarter of the Vref. To ease logic design, the Vref is only utilized during the third phase of conversion with the MSB capacitor of each DAC. The proposed scheme reduces DAC's average switching energy and the area by 94.44 % and 50 % in comparison with the conventional single-ended scheme. Furthermore, a novel 3-stage common-mode insensitive regenerative comparator is proposed to reduce non-linearity errors caused by common-mode voltage variations of DAC. The proposed single-ended ADC is simulated in a standard 65-nm CMOS technology with a resolution of 8-bit and sampling rate of 25 MS/s. The simulation results corroborate that the ADC consumes 124 µW power with 1.2 V supply voltage and attain a 7.23 effective number of bits, resulting in a 33fJ/conversion step FOM.