Area optimization for MPRM logic circuits based on improved multiple disturbances fireworks algorithm

• Published in: Applied mathematics and computation 2021-06, Vol.399, p.126008, Article 126008
• Main Authors: He, Zhen-xue, Pan, Yu-hua, Wang, Ke-jian, Xiao, Li-min, Wang, Xiang
• Format: Article
• Language: English
• Subjects: Area optimization; Fireworks algorithm; Latin hypercube sampling; MPRM logic circuits; Multiple disturbances
• ISSN: 0096-3003; 1873-5649
• DOI: 10.1016/j.amc.2021.126008

•An improved multiple disturbances fireworks algorithm is proposed to solve the three-valued variables combinatorial optimization problem.•An improved initial population construction method is proposed.•An MPRM circuit area optimization method is proposed, which uses the improved fireworks algorithm to search for the MPRM circuit with the minimum area.•Experimental results verify the effectiveness of our method in optimizing the area of MPRM circuits. Area optimization is one of the most important contents of circuit logic synthesis. In logical function expressions, mixed polarity Reed–Muller (MPRM) expansion produces a smaller area than Boolean expansion and fixed polarity Reed–Muller (FPRM) expansion. However, the area optimization for MPRM logic circuits is a combinatorial optimization problem, and the existing area optimization effect of MPRM logic circuits is poor. In this paper, an improved multiple disturbances fireworks algorithm is proposed to solve the combinatorial optimization problem of three-valued variables. Based on the ordinary fireworks algorithm, the algorithm we proposed initializes the individual of the fireworks population by introducing the Latin hypercube sampling model and introduces multiple disturbances in the process of iterative optimization of the population, so that the algorithm takes the global and local search into account, and achieves a good result. Moreover, we propose an MPRM logic circuits area optimization method, which uses the proposed improved multiple disturbances fireworks algorithm to search for the optimal polarity corresponding to MPRM logic circuits with minimum area. An adequate comparative analysis based on different MCNC benchmark circuits has been presented. The results of the experiment show that the method we proposed has a good effect on MPRM logic circuits area optimization.