A benchmark suite for designing combinational logic circuits via metaheuristics

The evolvable hardware literature reports several methods for the evolution of digital circuits. However, there is a large variability in the set of problems and the appropriate metrics used for the evaluation of the results. In this paper, we propose a set of representative problems to comparativel...

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Bibliographic Details
Published in:Applied soft computing 2020-06, Vol.91, p.106246, Article 106246
Main Authors: de Souza, Lucas Augusto Müller, da Silva, José Eduardo Henriques, Chaves, Luciano Jerez, Bernardino, Heder Soares
Format: Article
Language:English
Subjects:
Benchmark suite
Combinational logic circuits
Evolvable hardware
Performance evaluation
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Summary:The evolvable hardware literature reports several methods for the evolution of digital circuits. However, there is a large variability in the set of problems and the appropriate metrics used for the evaluation of the results. In this paper, we propose a set of representative problems to comparatively evaluate metaheuristics when designing Combinational Logic Circuits (CLCs). We also define a set of performance measurements and descriptive statistics to analyze the results found by the search techniques. As a case study, we compare Cartesian Genetic Programming variants applied to this domain. The results highlight the benefits of the proposed heterogeneous benchmark suite in the analysis of metaheuristics when designing CLCs. •A benchmark suite composed by a heterogeneous set of problems is proposed.•Metaheuristics can be analyzed when designing combinational logic circuits.•Performance measurements and statistical values are defined to compare the methods.•A case study shows the advantages of the proposed benchmark suite.
ISSN:1568-4946
1872-9681
DOI:10.1016/j.asoc.2020.106246