An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V- VCC negative-word-line DRAMs

A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V- V CC DRAMs with the negative-word-line (NWL) s...

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Bibliographic Details
Published in:Current applied physics 2003-12, Vol.3 (6), p.507-510
Main Authors: Min, Kyeong-Sik, Kim, Young-Hee, Kim, Daejeong, Kim, Dong Myeong, Cho, Seong-Ik, Ahn, Jin-Hong, Chung, Jin-Yong
Format: Article
Language:English
Subjects:
Large-current-output charge pump
Low-voltage charge pump
Low-voltage circuit
Low-voltage DRAM circuit
Low-voltage generator
Low-voltage memory circuit
Negative word line
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Summary:A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V- V CC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large.
ISSN:1567-1739
1878-1675
DOI:10.1016/j.cap.2003.09.004