FPGA architecture to perform symmetric extension on signals for handling border discontinuities in FIR filtering

• Published in: Computers & electrical engineering 2022-10, Vol.103, p.108307, Article 108307
• Main Authors: Kumar, Kasetty Praveen, Kanhe, Aniruddha
• Format: Article
• Language: English
• Subjects: Border discontinuities; Finite-impulse response filter; Finite-length signals; FPGA; Symmetric/anti-symmetric extension
• ISSN: 0045-7906; 1879-0755
• DOI: 10.1016/j.compeleceng.2022.108307

This paper proposes a generalized hardware architecture for performing the half-sample and whole-sample symmetric/anti-symmetric extension of a finite-length signal to handle the effect of border discontinuities. The symmetric extension is performed by duplicating the required number of data samples at the boundary followed by reflection about the symmetry axis. The proposed architecture comprises of a shift register that directly streams the data samples, and last-in-first-out (LIFO) buffers to duplicate the data samples at the boundaries. The symmetrically extended signal is obtained by selectively passing the outputs of shift register and LIFO buffers at required instants. Further, a two’s complement circuit is used to invert the data samples at the boundary to perform anti-symmetric extension. The proposed architecture is implemented on field-programmable gate-array (FPGA) to perform the half-sample symmetric extension to favor the low pass Daubechies-8 finite-impulse response (FIR) filter and whole-sample extension for bi-orthogonal 9 × 7 FIR filter with 9 low-pass and 7 high-pass coefficients. The implementation results show that the proposed architecture achieves a maximum operating clock frequency of 275 MHz and 300 MHz for half-sample and whole-sample extension, respectively. The resource utilization of proposed router architecture is approximately reduced by a factor of L (filter length) compared to the conventional router architectures that performs the signal extension by dynamically routing the data samples to the computational part of the FIR filter. The proposed architecture is compatible to various filter architectures without any speed penalty on the performance of FIR filters.