Simulating spin systems on IANUS, an FPGA-based computer

We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is co...

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Bibliographic Details
Published in:Computer physics communications 2008-02, Vol.178 (3), p.208-216
Main Authors: Belletti, F., Cotallo, M., Cruz, A., Fernández, L.A., Gordillo, A., Maiorano, A., Mantovani, F., Marinari, E., Martín-Mayor, V., Muñoz-Sudupe, A., Navarro, D., Pérez-Gaviro, S., Ruiz-Lorenzo, J.J., Schifano, S.F., Sciretti, D., Tarancón, A., Tripiccione, R., Velasco, J.L.
Format: Article
Language:English
Subjects:
Monte Carlo methods
Reconfigurable computing
Spin models
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Summary:We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O ( 100 ) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.
ISSN:0010-4655
1879-2944
DOI:10.1016/j.cpc.2007.09.006