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Failure analysis of ESD damage on interconnects in LCD GOA
•The root cause of GOA interconnects failure is determined to be ESD in VUV cleaning process.•Experiments exhibit the same failure and validate our analysis of failure.•ESD does not occur when two equal-length interconnects are irradiated simultaneously.•The failure severity versus the design parame...
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Published in: | Engineering failure analysis 2022-01, Vol.131, p.105892, Article 105892 |
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container_title | Engineering failure analysis |
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creator | Wang, Ye Fu, Guicui Tian, Pengcheng Wan, Bo Li, Jian Song, Yong Yu, Hongjun Xue, Hailin Che, Chuncheng Huang, Dongsheng Rong, Keyi Su, Yutai Chen, Weixiong Li, Xin |
description | •The root cause of GOA interconnects failure is determined to be ESD in VUV cleaning process.•Experiments exhibit the same failure and validate our analysis of failure.•ESD does not occur when two equal-length interconnects are irradiated simultaneously.•The failure severity versus the design parameter of interconnects is modeled.
Liquid crystal display (LCD) is likely to accumulate charge and incur ESD events due to the insulating glass plate. In our study, an ESD induced failure of interconnects in LCD gate driver on array (GOA) was analyzed. The monochrome pattern test was conducted to locate the failure site. The morphology of the failure site was characterized by SEM, EDS and FIB. Charge accumulation on long interconnects in the VUV-cleaning process, and subsequent discharging damage at narrow interconnect gaps were analyzed to be the root cause of failure. Furthermore, some specimens were designed to validate the analysis, design of experiments was performed to study the effects of the gap space and the interconnect length on the failure severity. Based on the experimental data, a logistic model was developed to model the failure severity, which can help to provide suggestions for designs to reduce the incidence of failures. |
doi_str_mv | 10.1016/j.engfailanal.2021.105892 |
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Liquid crystal display (LCD) is likely to accumulate charge and incur ESD events due to the insulating glass plate. In our study, an ESD induced failure of interconnects in LCD gate driver on array (GOA) was analyzed. The monochrome pattern test was conducted to locate the failure site. The morphology of the failure site was characterized by SEM, EDS and FIB. Charge accumulation on long interconnects in the VUV-cleaning process, and subsequent discharging damage at narrow interconnect gaps were analyzed to be the root cause of failure. Furthermore, some specimens were designed to validate the analysis, design of experiments was performed to study the effects of the gap space and the interconnect length on the failure severity. Based on the experimental data, a logistic model was developed to model the failure severity, which can help to provide suggestions for designs to reduce the incidence of failures.</description><identifier>ISSN: 1350-6307</identifier><identifier>EISSN: 1873-1961</identifier><identifier>DOI: 10.1016/j.engfailanal.2021.105892</identifier><language>eng</language><publisher>Elsevier Ltd</publisher><subject>Electrostatic Discharge (ESD) ; Gate driver on array (GOA) ; Interconnects failure ; Liquid Crystal Display (LCD) ; VUV cleaning</subject><ispartof>Engineering failure analysis, 2022-01, Vol.131, p.105892, Article 105892</ispartof><rights>2021 Elsevier Ltd</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c321t-48f1d7e317d19c1d17bf05a78fe2789525683811c34f2a7f488f64d551e94d33</citedby><cites>FETCH-LOGICAL-c321t-48f1d7e317d19c1d17bf05a78fe2789525683811c34f2a7f488f64d551e94d33</cites><orcidid>0000-0001-7756-2560 ; 0000-0002-2909-5715</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Wang, Ye</creatorcontrib><creatorcontrib>Fu, Guicui</creatorcontrib><creatorcontrib>Tian, Pengcheng</creatorcontrib><creatorcontrib>Wan, Bo</creatorcontrib><creatorcontrib>Li, Jian</creatorcontrib><creatorcontrib>Song, Yong</creatorcontrib><creatorcontrib>Yu, Hongjun</creatorcontrib><creatorcontrib>Xue, Hailin</creatorcontrib><creatorcontrib>Che, Chuncheng</creatorcontrib><creatorcontrib>Huang, Dongsheng</creatorcontrib><creatorcontrib>Rong, Keyi</creatorcontrib><creatorcontrib>Su, Yutai</creatorcontrib><creatorcontrib>Chen, Weixiong</creatorcontrib><creatorcontrib>Li, Xin</creatorcontrib><title>Failure analysis of ESD damage on interconnects in LCD GOA</title><title>Engineering failure analysis</title><description>•The root cause of GOA interconnects failure is determined to be ESD in VUV cleaning process.•Experiments exhibit the same failure and validate our analysis of failure.•ESD does not occur when two equal-length interconnects are irradiated simultaneously.•The failure severity versus the design parameter of interconnects is modeled.
Liquid crystal display (LCD) is likely to accumulate charge and incur ESD events due to the insulating glass plate. In our study, an ESD induced failure of interconnects in LCD gate driver on array (GOA) was analyzed. The monochrome pattern test was conducted to locate the failure site. The morphology of the failure site was characterized by SEM, EDS and FIB. Charge accumulation on long interconnects in the VUV-cleaning process, and subsequent discharging damage at narrow interconnect gaps were analyzed to be the root cause of failure. Furthermore, some specimens were designed to validate the analysis, design of experiments was performed to study the effects of the gap space and the interconnect length on the failure severity. Based on the experimental data, a logistic model was developed to model the failure severity, which can help to provide suggestions for designs to reduce the incidence of failures.</description><subject>Electrostatic Discharge (ESD)</subject><subject>Gate driver on array (GOA)</subject><subject>Interconnects failure</subject><subject>Liquid Crystal Display (LCD)</subject><subject>VUV cleaning</subject><issn>1350-6307</issn><issn>1873-1961</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><recordid>eNqNkMtKAzEUhoMoWKvvEB9gak4ymSTuyvSiUOjC7kPMpaS0GUmq0Lc3pS66dHUu8P2c8yH0DGQCBLqX3cSnbTBxb5LZTyihUPdcKnqDRiAFa0B1cFt7xknTMSLu0UMpO0KIoApG6HVR2e_s8Zk_lVjwEPD8Y4adOZitx0PCMR19tkNK3h5LnfCqn-HlevqI7oLZF__0V8dos5hv-rdmtV6-99NVYxmFY9PKAE54BsKBsuBAfAbCjZDBUyEVp7yTTAJY1gZqRGilDF3rOAevWsfYGKlLrM1DKdkH_ZXjweSTBqLPDvROXznQZwf64qCy_YX19b6f6LMuNvpkvYu5fqPdEP-R8gsBwWi5</recordid><startdate>202201</startdate><enddate>202201</enddate><creator>Wang, Ye</creator><creator>Fu, Guicui</creator><creator>Tian, Pengcheng</creator><creator>Wan, Bo</creator><creator>Li, Jian</creator><creator>Song, Yong</creator><creator>Yu, Hongjun</creator><creator>Xue, Hailin</creator><creator>Che, Chuncheng</creator><creator>Huang, Dongsheng</creator><creator>Rong, Keyi</creator><creator>Su, Yutai</creator><creator>Chen, Weixiong</creator><creator>Li, Xin</creator><general>Elsevier Ltd</general><scope>AAYXX</scope><scope>CITATION</scope><orcidid>https://orcid.org/0000-0001-7756-2560</orcidid><orcidid>https://orcid.org/0000-0002-2909-5715</orcidid></search><sort><creationdate>202201</creationdate><title>Failure analysis of ESD damage on interconnects in LCD GOA</title><author>Wang, Ye ; Fu, Guicui ; Tian, Pengcheng ; Wan, Bo ; Li, Jian ; Song, Yong ; Yu, Hongjun ; Xue, Hailin ; Che, Chuncheng ; Huang, Dongsheng ; Rong, Keyi ; Su, Yutai ; Chen, Weixiong ; Li, Xin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c321t-48f1d7e317d19c1d17bf05a78fe2789525683811c34f2a7f488f64d551e94d33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Electrostatic Discharge (ESD)</topic><topic>Gate driver on array (GOA)</topic><topic>Interconnects failure</topic><topic>Liquid Crystal Display (LCD)</topic><topic>VUV cleaning</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Wang, Ye</creatorcontrib><creatorcontrib>Fu, Guicui</creatorcontrib><creatorcontrib>Tian, Pengcheng</creatorcontrib><creatorcontrib>Wan, Bo</creatorcontrib><creatorcontrib>Li, Jian</creatorcontrib><creatorcontrib>Song, Yong</creatorcontrib><creatorcontrib>Yu, Hongjun</creatorcontrib><creatorcontrib>Xue, Hailin</creatorcontrib><creatorcontrib>Che, Chuncheng</creatorcontrib><creatorcontrib>Huang, Dongsheng</creatorcontrib><creatorcontrib>Rong, Keyi</creatorcontrib><creatorcontrib>Su, Yutai</creatorcontrib><creatorcontrib>Chen, Weixiong</creatorcontrib><creatorcontrib>Li, Xin</creatorcontrib><collection>CrossRef</collection><jtitle>Engineering failure analysis</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Wang, Ye</au><au>Fu, Guicui</au><au>Tian, Pengcheng</au><au>Wan, Bo</au><au>Li, Jian</au><au>Song, Yong</au><au>Yu, Hongjun</au><au>Xue, Hailin</au><au>Che, Chuncheng</au><au>Huang, Dongsheng</au><au>Rong, Keyi</au><au>Su, Yutai</au><au>Chen, Weixiong</au><au>Li, Xin</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Failure analysis of ESD damage on interconnects in LCD GOA</atitle><jtitle>Engineering failure analysis</jtitle><date>2022-01</date><risdate>2022</risdate><volume>131</volume><spage>105892</spage><pages>105892-</pages><artnum>105892</artnum><issn>1350-6307</issn><eissn>1873-1961</eissn><abstract>•The root cause of GOA interconnects failure is determined to be ESD in VUV cleaning process.•Experiments exhibit the same failure and validate our analysis of failure.•ESD does not occur when two equal-length interconnects are irradiated simultaneously.•The failure severity versus the design parameter of interconnects is modeled.
Liquid crystal display (LCD) is likely to accumulate charge and incur ESD events due to the insulating glass plate. In our study, an ESD induced failure of interconnects in LCD gate driver on array (GOA) was analyzed. The monochrome pattern test was conducted to locate the failure site. The morphology of the failure site was characterized by SEM, EDS and FIB. Charge accumulation on long interconnects in the VUV-cleaning process, and subsequent discharging damage at narrow interconnect gaps were analyzed to be the root cause of failure. Furthermore, some specimens were designed to validate the analysis, design of experiments was performed to study the effects of the gap space and the interconnect length on the failure severity. Based on the experimental data, a logistic model was developed to model the failure severity, which can help to provide suggestions for designs to reduce the incidence of failures.</abstract><pub>Elsevier Ltd</pub><doi>10.1016/j.engfailanal.2021.105892</doi><orcidid>https://orcid.org/0000-0001-7756-2560</orcidid><orcidid>https://orcid.org/0000-0002-2909-5715</orcidid></addata></record> |
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subjects | Electrostatic Discharge (ESD) Gate driver on array (GOA) Interconnects failure Liquid Crystal Display (LCD) VUV cleaning |
title | Failure analysis of ESD damage on interconnects in LCD GOA |
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